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3959
A3959SLB (SOIC)
CHARGE PUMP
DMOS FULL-BRIDGE PWM MOTOR DRIVER
Designed for pulse-width modulated (PWM) current control of dc motors, the A3959SB, A3959SLB, and A3959SLP are capable of output currents to 3 A and operating voltages to 50 V. Internal fixed off-time PWM current-control timing circuitry can be adjusted via control inputs to operate in slow, fast, and mixed current-decay modes. PHASE and ENABLE input terminals are provided for use in controlling the speed and direction of a dc motor with externally applied PWM-control signals. Internal synchronous rectification control circuitry is provided to reduce power dissipation during PWM operation. Internal circuit protection includes thermal shutdown with hysteresis, undervoltage monitoring of supply and charge pump, and crossover-current protection. Special power-up sequencing is not required. The A3959SB/SLB/SLP is a choice of three power packages, a 24-pin plastic DIP with a copper batwing tab (package suffix `B'), a 24-lead plastic SOIC with a copper batwing tab (package suffix `LB'), and a thin (<1.2 mm) 28-lead plastic TSSOP with an exposed thermal pad (suffix `LP'). In all cases, the power tab is at ground potential and needs no electrical isolation. Each package is available in a lead-
Data Sheet 29319.37E
CP CP2 CP1 PHASE ROSC GROUND GROUND LOGIC SUPPLY ENABLE PFD2 BLANK PFD1
1 2 3 4 5
24 23 NC 22 21 VBB 20 19 18
VREG SLEEP NO CONNECTION OUTB LOAD SUPPLY GROUND GROUND SENSE OUTA NO CONNECTION EXT MODE REF
Dwg. PP-069-4
6 7 8 9 9 V DD
LOGIC
17 16
PWM TIMER
10 11 12
NC
15 14
/10
13
Note that the A3959SLB(SOIC), A3959SB (DIP), and A3959SLP (TSSOP) do not share a common terminal assignment.
ABSOLUTE MAXIMUM RATINGS
Load Supply Voltage, VBB ......................... 50 V Output Current, IOUT (Repetitive) ........... 3.0 A (Peak, <3 s) ................................... 6.0 A Logic Supply Voltage, VDD ....................... 7.0 V Logic Input Voltage Range, VIN (Continuous) ............ -0.3 V to VDD + 0.3 V (tw <30 ns) ............... -1.0 V to VDD + 1.0 V Sense Voltage, VS (Continuous) .............. 0.5 V (tw <3 s) ........................................... 2.5 V Reference Voltage, VREF ............................ VDD Package Power Dissipation (TA = 25C), PD A3959SB ........................................ 3.3 W* A3959SLB ...................................... 2.5 W* A3959SLP ...................................... 3.1 W* Operating Temp. Range, TA .... -20C to +85C Junction Temperature, TJ ..................... +150C Storage Temp. Range, TS ..... -55C to +150C Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150C.
free version (100% matte tin leadframe). FEATURES
s s s s s s s 3 A, 50 V Output Rating Low rDS(on) Outputs (270 m, Typical) Mixed, Fast, and Slow Current-Decay Modes Synchronous Rectification for Low Power Dissipation Internal UVLO and Thermal-Shutdown Circuitry Crossover-Current Protection Internal Oscillator for Digital PWM Timing
Package 24-pin batwing DIP 24-pin batwing DIP; Lead-free 24-lead batwing SOIC 24-lead batwing SOIC; Lead-free 28-lead thin shrink SOIC 28-lead thin shrink SOIC; Lead-free RJA* 38C/W 38C/W 50C/W 50C/W 40C/W 40C/W R JT 6C/W 6C/W 6C/W 6C/W -- --
Always order by complete part number:
Part Number A3959SB A3959SB-T A3959SLB A3959SLB-T A3959SLP A3959SLP-T
* Double-sided board, one square inch copper each side. See also, Layout, page 7.
3959 DMOS FULL-BRIDGE PWM MOTOR DRIVER
FUNCTIONAL BLOCK DIAGRAM
VDD LOGIC SUPPLY
CHARGE PUMP BANDGAP VDD CREG TSD
VBB
+
CP1 CP2
LOAD SUPPLY BANDGAP REGULATOR VREG
UNDERVOLTAGE & FAULT DETECT
CHARGE PUMP
SLEEP EXT MODE PHASE ENABLE CONTROL LOGIC
GATE DRIVE
CP
OUTA
OUTB SENSE
ZERO CURRENT DETECT
TO VDD BLANK PFD1 PFD2 ROSC OSC
CURRENT SENSE
CS RS
PWM TIMER
REFERENCE BUFFER & /10
REF
VREF
Dwg. FP-048-2A
CP2 CP1 PHASE ROSC GROUND GROUND GROUND GROUND LOGIC SUPPLY ENABLE PFD2 BLANK
1 2 3 4 5
CHARGE PUMP
24 23 22 21 VBB 20 19 18 17
CP VREG SLEEP OUTB LOAD SUPPLY GROUND GROUND SENSE OUTA EXT MODE REF PFD1
Dwg. PP-069-5A
A3959SB (DIP)
Note that the A3959SLB (SOIC), A3959SB (DIP), and A3959SLP (TSSOP) do not share a common terminal assignment.
6 7 8 9 9 10 11 12 V DD
LOGIC
16 15
/10
PWM TIMER
14 13
2
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright (c) 2001, 2003 Allegro MicroSystems, Inc.
3959 DMOS FULL-BRIDGE PWM MOTOR DRIVER
ELECTRICAL CHARACTERISTICS at TA = +25C, VBB = 50 V, VDD = 5.0 V, VSENSE = 0.5 V, fPWM < 50 kHz (unless noted otherwise)
Limits Characteristics Output Drivers Load Supply Voltage Range Output Leakage Current Output On Resistance Crossover Delay Body Diode Forward Voltage Load Supply Current VF IBB Source diode, IF = -3 A Sink diode, IF = 3 A fPWM < 50 kHz Charge pump on, outputs disabled Sleep Mode Control Logic Logic Supply Voltage Range Logic Input Voltage Logic Input Current (all inputs except ENABLE) ENABLE Input Current Internal OSC frequency Reference Input Volt. Range Reference Input Current Comparator Input Offset Volt. VDD VIN(1) VIN(0) IIN(1) IIN(0) IIN(1) IIN(0) fOSC VREF IREF VIO VIN = 2.0 V VIN = 0.8 V VIN = 2.0 V VIN = 0.8 V ROSC shorted to GROUND ROSC = 51 k Operating VREF = VDD VREF = 0 V Operating 4.5 2.0 - - - - - 3.25 3.65 0.0 - - 5.0 - - <1.0 <-2.0 40 16 4.25 4.25 - - 5.0 5.5 - 0.8 20 -20 100 40 5.25 4.85 VDD 1.0 - V V V A A A A MHz MHz V A mV VBB IDSS rDS(on) Operating During sleep mode VOUT = VBB VOUT = 0 V Source driver, IOUT = -3 A Sink driver, IOUT = 3 A 9.5 0 - - - - 300 - - - - - - - <1.0 <-1.0 270 270 600 - - 4.0 2.0 - 50 50 20 -20 300 300 1000 1.6 1.6 7.0 5.0 20 V V A A m m ns V V mA mA A Symbol Test Conditions Min. Typ. Max. Units
Continued next page ...
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3959 DMOS FULL-BRIDGE PWM MOTOR DRIVER
ELECTRICAL CHARACTERISTICS at TA = +25C, VBB = 50 V, VDD = 5.0 V, VSENSE = 0.5 V, fPWM < 50 kHz (unless noted otherwise), continued.
Limits Characteristics Control Logic Reference Divider Ratio Gm Error (Note 3) Propagation Delay Times tpd - EGm VREF = VDD VREF = 0.5 V 0.5 Ein to 0.9 Eout: PWM change to source on PWM change to source off PWM change to sink on PWM change to sink off - - - 600 50 600 50 - - Increasing VDD fPWM < 50 kHz Sleep Mode 3.90 0.05 - - 10 - - 750 150 750 100 165 15 4.2 0.10 6.0 - - 4.0 14 1200 350 1200 150 - - 4.45 - 10 2.0 - % % ns ns ns ns C C V V mA mA Symbol Test Conditions Min. Typ. Max. Units
Thermal Shutdown Temp. Thermal Shutdown Hysteresis UVLO Enable Threshold UVLO Hysteresis Logic Supply Current
TJ TJ UVLO UVLO IDD
NOTES: 1. Typical Data is for design information only. 2. Negative current is defined as coming out of (sourcing) the specified device terminal. 3. Gm error = ([VREF/10] - VSENSE)/(VREF/10) where VSENSE = ITRIP*RS.
4
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
3959 DMOS FULL-BRIDGE PWM MOTOR DRIVER
FUNCTIONAL DESCRIPTION
VREG. This internally generated voltage is used to operate the sink-side DMOS outputs. The VREG terminal should be decoupled with a 0.22 F capacitor to ground. VREG is internally monitored and in the case of a fault condition, the outputs of the device are disabled. Charge Pump. The charge pump is used to generate a gate-supply voltage greater than VBB to drive the sourceside DMOS gates. A 0.22 F ceramic capacitor should be connected between CP1 and CP2 for pumping purposes. A 0.22 F ceramic capacitor should be connected between CP and VBB to act as a reservoir to operate the high-side DMOS devices. The CP voltage is internally monitored and, in the case of a fault condition, the source outputs of the device are disabled. PHASE Logic. The PHASE input terminal determines if the device is operating in the "forward" or "reverse" state. PHASE 0 1 OUTA Low High OUTB High Low EXT MODE Logic. When using external PWM current control, the EXT MODE input determines the current path during the chopped cycle. With EXT MODE low, fast decay mode, the opposite pair of selected outputs will be enabled during the off cycle. With EXT MODE high, slow decay mode, both sink drivers are on with ENABLE low. EXT MODE 0 1 Decay Fast Slow
Current Regulation. Load current is regulated by an internal fixed off-time PWM control circuit. When the outputs of the DMOS H bridge are turned on, the current increases in the motor winding until it reaches a trip value determined by the external sense resistor (RS) and the applied analog reference voltage (VREF): ITRIP = VREF/10RS At the trip point, the sense comparator resets the sourceenable latch, turning off the source driver. The load inductance then causes the current to recirculate for the fixed off-time period. The current path during recirculation is determined by the configuration of slow/ mixed/fast current-decay mode via PFD1 and PFD2. Oscillator. The PWM timer is based on an internal oscillator set by a resistor connected from the ROSC terminal to VDD. Typical value of 4 MHz is set with a 51 k resistor. The allowable range of the resistor is from 20 k to 100 k. fOSC = 204 x 109/ROSC. If ROSC is not pulled up to VDD, it must be shorted to ground. Fixed Off Time. The A3959 is set for a fixed off time of 96 cycles of the internal oscillator, typically 24 s with a 4 MHz oscillator.
ENABLE Logic. The ENABLE input terminal allows external PWM. ENABLE high turns on the selected sinksource pair. ENABLE low switches off the source driver or the source and sink driver, depending on EXT MODE, and the load current decays. If ENABLE is kept high, the current will rise until it reaches the level set by the internal current-control circuit. ENABLE 0 1 Outputs Chopped On
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5
3959 DMOS FULL-BRIDGE PWM MOTOR DRIVER
FUNCTIONAL DESCRIPTION (continued)
Internal Current-Control Mode. Inputs PFD1 and PFD2 determine the current-decay method after an overcurrent event is detected at the SENSE input. In slow-decay mode, both sink drivers are turned on for the fixed off-time period. Mixed-decay mode starts out in fast-decay mode for a portion (15% or 48%) of the fixed off time, and then is followed by slow decay for the remainder of the period. PFD2 0 0 1 1 PFD1 0 1 0 1 % toff 0 15 48 100 Decay Slow Mixed Mixed Fast Synchronous Rectification. When a PWM off cycle is triggered, either by an ENABLE chop command or internal fixed off-time cycle, load current will recirculate according to the decay mode selected by the control logic. The A3959 synchronous rectification feature will turn on the appropriate pair of DMOS outputs during the current decay and effectively short out the body diodes with the low rDS(on) driver. This will reduce power dissipation significantly and can eliminate the need for external Schottky diodes. Synchronous rectification will prevent reversal of load current by turning off all outputs when a zero-current level is detected. Shutdown. In the event of a fault (excessive junction temperature, or low voltage on CP or VREG) the outputs of the device are disabled until the fault condition is removed. At power up, and in the event of low VDD, the UVLO circuit disables the drivers. Braking. The braking function is implemented by driving the device in slow-decay mode via EXTMODE and applying an enable chop command. Because it is possible to drive current in either direction through the DMOS drivers, this configuration effectively shorts out the motor-generated BEMF as long as the ENABLE chop mode is asserted. It is important to note that the internal PWM current-control circuit will not limit the current when braking, because the current does not flow through the sense resistor. The maximum brake current can be approximated by VBEMF/RL. Care should be taken to ensure that the maximum ratings of the device are not exceeded in worst-case braking situations of high speed and high inertial loads. SLEEP Logic. The SLEEP input terminal is used to minimize power consumption when when not in use. This disables much of the internal circuitry including the regulator and charge pump. Logic low will put the device into sleep mode, logic high will allow normal operation.
PWM Blank Timer. When a source driver turns on, a current spike occurs due to the reverse-recovery currents of the clamp diodes and/or switching transients related to distributed capacitance in the load. To prevent this current spike from erroneously resetting the source-enable latch, the sense comparator is blanked. The blank timer runs after the off-time counter to provide the blanking function. The blank timer is reset when ENABLE is chopped or PHASE is changed. For external PWM control, a PHASE change or ENABLE on will trigger the blanking function. The duration is determined by the BLANK input and the oscilator. BLANK 0 1 tblank 6/fosc 12/fosc
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115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
3959 DMOS FULL-BRIDGE PWM MOTOR DRIVER
FUNCTIONAL DESCRIPTION (continued)
Current Sensing. To minimize inaccuracies in sensing the ITRIP current level, which may be caused by ground trace IR drops, the sense resistor should have an independent ground return to the ground terminal of the device. For low-value sense resistors the IR drops in the PCB sense resistor's traces can be significant and should be taken into account. The use of sockets should be avoided as they can introduce variation in RS due to their contact resistance. The maximum value of RS is given as RS 0.5/ITRIP where ITRIP 3.0 A. Thermal Protection. Circuitry turns off all drivers when the junction temperature reaches 165C typically. It is intended only to protect the device from failures due to excessive junction temperatures and should not imply that output short circuits are permitted. Thermal shutdown has a hysteresis of approximately 15C.
5
SUFFIX 'B', RJA = 26C/W SUFFIX 'LP', RJA = 28C/W SUFFIX 'LB', RJA = 35C/W MULTI-LAYER HIGH-K BOARD
Layout. A star ground system located close to the driver is recommended. The printed wiring board should use a heavy ground plane. For optimum electrical and thermal performance*, the driver should be soldered directly onto the board. The ground side of RS should have an individual path to the ground terminals of the device. This path should be as short as is possible physically and should not have any other components connected to it. It is recommended that a 0.1 F capacitor be placed between SENSE and ground as close to the device as possible; the load supply terminal, VBB, should be decoupled with an electrolytic capacitor (> 47 F is recommended) placed as close to the device as is possible. On the 28-lead TSSOP package, the copper ground plane located under the exposed thermal pad is typically used as a star ground.
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
4
* The thermal resistance, RJA, and absolute maximum allowable package power dissipation specified on page 1 is measured on a typical two-sided PCB with one square inch copper ground area on each side. With minimal copper on a single-sided PCB (worst-case), the `B' package RJA is 40C/W, `LB' is 77C/W, and `LP' is 80C/W. See also, Application Note 29501.5, Improving Batwing Power Dissipation. For specification purposes, the multi-layer high-K board performance graphed here is per JEDEC Standard JESD51.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current.
3
2
1 SUFFIX 'B', RJA = 38C/W
SUFFIX 'LP', RJA = 40C/W SUFFIX 'LB', RJA = 50C/W DOUBLE-SIDED BOARD, 1 SQ. IN. COPPER EA. SIDE
0
25
50
75 100 TEMPERATURE IN C
125
150
Dwg. GP-049-6
Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use.
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3959 DMOS FULL-BRIDGE PWM MOTOR DRIVER
Terminal List
LB Terminal Name CP CP1 & CP2 NC PHASE ROSC GROUND LOGIC SUPPLY ENABLE NC PFD2 BLANK PFD1 REF EXT MODE NO CONNECT OUTA NC SENSE NC GROUND LOAD SUPPLY OUTB NO CONNECT SLEEP VREG GROUND Terminal Description Reservoir capacitor (typically 0.22 F) The charge pump capacitor (typically 0.22 F) No (internal) connection Logic input for direction control Oscillator resistor Grounds VDD, the low voltage (typically 5 V) supply Logic input for enable control No (internal) connection Logic-level input for fast decay Logic-level input for blanking control Logic-level input for fast decay VREF, the load current reference input voltage Logic input for PWM mode control No (Internal) connection One of two DMOS bridge outputs to the motor No (internal) connection Sense resistor No (internal) connection Grounds VBB, the high-current, 9.5 V to 50 V, motor supply One of two DMOS bridge outputs to the motor No (Internal) connection Logic-level Input for sleep operation Regulator decoupling capacitor (typically 0.22 F) Ground (SOIC) 1 2&3 -- 4 B (DIP) 24 1&2 -- 3 LP (TSSOP) 1 2&3 4 5 6 7, 8* 9 10 11 12 13 14 15 16 17 18 19, 20 21 22 -- 23 24 25 26 27 28*
5 4 6, 7 5, 6, 7, 8* 8 9 - 10 11 12 13 14 15 16 - 17 - 9 10 - 11 12 13 14 15 -- 16 - 17 -
18, 19 18, 19* 20 20 21 22 23 24 -- 21 -- 22 23 --
* For the A3959SB (DIP) only, there is an indeterminate resistance between the substrate grounds (pins 6, 7, 18, and 19) and the grounds at pins 5 and 8. Pins 5 and 8, and 6, 7, 18, or 19 must be connected together externally. For the A3959SLP (TSSOP) the grounds at terminals 7, 8, and 28 should be connected together at the exposed pad beneath the device.
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115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
3959 DMOS FULL-BRIDGE PWM MOTOR DRIVER
A3959SB
Dimensions in Inches (controlling dimensions)
0.014 0.008
24
NOTE 1
13
0.430 0.280 0.240
MAX
0.300
BSC
1
0.070 0.045
6
7 1.280 1.230
0.100
BSC
12
0.005
MIN
0.210
MAX
0.015
MIN
0.150 0.115 0.022 0.014
Dwg. MA-001-25A in
Dimensions in Millimeters (for reference only)
24
NOTE 1
13
0.355 0.204
10.92 7.11 6.10
MAX
7.62
BSC
1
1.77 1.15
6
7 32.51 31.24
2.54
BSC
12
0.13
MIN
5.33
MAX
0.39
MIN
3.81 2.93 0.558 0.356
Dwg. MA-001-25A mm
NOTES: 1. 2. 3. 4. 5.
Webbed lead frame. Leads 6, 7, 18, and 19 are internally one piece. Exact body and lead configuration at vendor's option within limits shown. Lead spacing tolerance is non-cumulative. Lead thickness is measured at seating plane or below. Supplied in standard sticks/tubes of 15 devices.
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3959 DMOS FULL-BRIDGE PWM MOTOR DRIVER
A3959SLB
24 13 0.0125 0.0091
0.2992 0.2914
0.419 0.394 0.050 0.016
Dimensions in Inches (for reference only)
0.020 0.013
1
2
3
0.6141 0.5985
0.050
BSC NOTE 1 NOTE 3
0 TO 8
0.0926 0.1043 0.0040 MIN.
Dwg. MA-008-25A in
24
0.32 0.23
7.60 7.40
10.65 10.00 1.27 0.40
Dimensions in Millimeters (controlling dimensions)
0.51 0.33
1
2
3
15.60 15.20
1.27
BSC NOTE 1 NOTE 3
0 TO 8
2.65 2.35 0.10 MIN.
Dwg. MA-008-25A mm
NOTES: 1. 2. 3. 4.
Exact body and lead configuration at vendor's option within limits shown. Lead spacing tolerance is non-cumulative. Webbed lead frame. Leads 6, 7, 18, and 19 are internally one piece. Supplied in standard sticks/tubes of 31 devices or add "TR" to part number for tape and reel.
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115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
3959 DMOS FULL-BRIDGE PWM MOTOR DRIVER
A3959SLP 28-pin TSSOP
9.8 9.6 28
.386 .378
8" 0" 0.20 .008 0.09 .004
4.5 4.3 6.6 6.2 .260 .244
.177 .169
A 3 .118 BSC 1 .039 REF 5 .200 BSC
1
2
0.75 .030 0.45 .018
0.25 .010 BSC Seating Plane Gauge Plane
0.30 .012 0.19 .007
0.65 .026 BSC
1.20 .047 MAX 0.15 .006 0.00 .000
0.30 .012 BSC
0.65 .026 BSC
6.6 .260 BSC
2.7 .106 BSC
4.5 .138 BSC 0.75 .030 BSC Dimensions in millimeters U.S. Customary dimensions (in.) in brackets, for reference only A Exposed thermal pad (bottom surface)
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3959 DMOS FULL-BRIDGE PWM MOTOR DRIVER
MOTOR DRIVERS
Output Ratings* Part Number INTEGRATED CIRCUITS FOR BRUSHLESS DC MOTORS 3-Phase Power MOSFET Controller -- 28 V 3933 3-Phase Power MOSFET Controller -- 40 V 3935 3-Phase Power MOSFET Controller -- 50 V 3932 & 3938 3-Phase Back-EMF Controller/Driver 900 mA 14 V 8904 3-Phase PWM Current-Controlled DMOS Driver 3.0 A 50 V 3936 INTEGRATED BRIDGE DRIVERS FOR DC AND BIPOLAR STEPPER MOTORS PWM Current-Controlled Dual Full Bridge 500 mA 18 V 3965 Dual Full Bridge with Protection & Diagnostics 500 mA 30 V 3976 PWM Current-Controlled Dual Full Bridge 650 mA 30 V 3966 PWM Current-Controlled Dual Full Bridge 650 mA 30 V 3968 Microstepping Translator/Dual Full Bridge 750 mA 30 V 3967 PWM Current-Controlled Dual Full Bridge 750 mA 45 V 2916 PWM Current-Controlled Dual Full Bridge 750 mA 45 V 2919 PWM Current-Controlled Dual Full Bridge 750 mA 45 V 6219 PWM Current-Controlled Dual Full Bridge 800 mA 33 V 3964 PWM Current-Controlled Dual DMOS Full Bridge 1.0 A 35 V 3973 PWM Current-Controlled Full Bridge 1.3 A 50 V 3953 PWM Current-Controlled Dual Full Bridge 1.5 A 45 V 2917 PWM Current-Controlled DMOS Full Bridge 1.5 A 50 V 3948 PWM Current-Controlled Microstepping Full Bridge 1.5 A 50 V 3955 PWM Current-Controlled Microstepping Full Bridge 1.5 A 50 V 3957 PWM Current-Controlled Dual DMOS Full Bridge 1.5 A 50 V 3972 PWM Current-Controlled Dual DMOS Full Bridge 1.5 A 50 V 3974 PWM Current-Controlled Full Bridge 2.0 A 50 V 3952 PWM Current-Controlled DMOS Full Bridge 2.0 A 50 V 3958 Microstepping Translator/Dual DMOS Full Bridge 2.5 A 35 V 3977 PWM Current-Controlled DMOS Full Bridge 3.0 A 50 V 3959 UNIPOLAR STEPPER MOTOR & OTHER DRIVERS Unipolar Stepper-Motor Translator/Driver 1.0 A 46 V 7050 Unipolar Stepper-Motor Translator/Driver 1.25 A 50 V 5804 Unipolar Stepper-Motor Quad Drivers 1.5 A 46 V 7024 & 7029 Unipolar Microstepper-Motor Quad Driver 1.5 A 46 V 7042 Unipolar Stepper-Motor Quad Driver 1.8 A 50 V 2540 Unipolar Stepper-Motor Translator/Driver 2.0 A 46 V 7051 Unipolar Stepper-Motor Quad Driver 3.0 A 46 V 7026 Unipolar Microstepper-Motor Quad Driver 3.0 A 46 V 7044 Unipolar Stepper-Motor Translator/Driver 3.0 A 46 V 7052 * Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits or over-current protection voltage limits. Negative current is defined as coming out of (sourcing) the output. Complete part number includes additional characters to indicate operating temperature range and package style. Also, see 3175, 3177, 3235, and 3275 Hall-effect sensors for use with brushless dc motors. Function
12
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000

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